
The CD4027 is a edge-triggered dual JK flip-flop which features independent set-direct (SD),clear-direct(CD),clock (CP)inputs and outputs(Q,Q).Data is accepted when CP is LOW,and transferred to the output on thepositive-going edge of the clock.The active HIGH asynchronous clear-direct (CD)and set-direct (SD)inputs areindependent and override the J,K,and CP inputs.The outputs are buffered for best system performance.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unusedinputs must be connected to VDD,VSS,or another input.
Features
Wide supply voltage range from 3V to 15V
Fully static operation
5V,10V,and 15V parametric ratings
Standardized symmetrical output characteristics
Specified from-40C to+105C
Packaging information:DIP16/SOP16/TSSOP16

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